Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

Ultra-pure crystalline silica — the original source of the silicon atoms in every chip. The highest grades come from a few deposits, most famously Spruce Pine, NC.

Mined, crushed, and chemically/physically purified to remove metal impurities to parts-per-billion for crucible- and optics-grade material.

~99% pure silicon, the bulk commodity form. Most output goes to aluminum alloys and silicones; only a sliver is purified further for electronics.

Carbothermic reduction of quartz with carbon in a submerged-arc furnace at ~2000 °C — extremely energy-intensive.

Silicon purified to eleven nines (99.999999999%) — feedstock for single-crystal ingots. A different, far purer product than solar-grade poly.

MG-Si → trichlorosilane → distilled → deposited as ultrapure polysilicon via the Siemens CVD process. Famously energy-hungry.

A defect-free single crystal of silicon, sliced and polished into mirror-flat 300 mm discs — the canvas every transistor is built on.

Polysilicon pulled into a single crystal (Czochralski), then sliced, lapped, etched, and chemically-mechanically polished to atomic flatness.

The machines that print the smallest features using 13.5 nm EUV light — the hardest tool in the stack and a sole-supplier chokepoint.

Built by ASML from ~100,000 parts incl. Zeiss optics and a Cymer tin-plasma source; Low-NA ~$180M, High-NA ~$380M; 48 EUV systems shipped in 2025.

The parallel design rail: electronic design automation (EDA) software, licensed IP cores, and the photomask set that encodes the design onto silicon.

Designed on Synopsys/Cadence tools with Arm and third-party IP; a 3nm design NRE is $400–600M, resolving into a ~$15M mask set.

The consumable chemistry of fabrication: neon for the lasers, ultra-pure etch/deposition gases, photoresist, CMP slurry, and dopants.

Neon is a byproduct of legacy steel plants; specialty gases and resists come from Linde, Air Liquide, JSR, TOK, etc.

High-bandwidth memory: stacks of DRAM die bonded beside the logic die in the package. The naive chain omits it; it's a huge share of accelerator value.

SK Hynix, Samsung, and Micron stack and TSV-bond DRAM dies; co-packaged with the logic die via CoWoS.

The back-end that turns a die into an accelerator: silicon interposer, ABF build-up film, FC-BGA substrate, and the CoWoS assembly that ties logic + memory together.

TSMC CoWoS bonds die + HBM onto a silicon interposer; Ajinomoto ABF film and Ibiden/Unimicron/Shinko substrates underneath; OSATs do final test.