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Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

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TSMC

https://www.tsmc.com/ ↗

Leading-edge fab + advanced packaging (CoWoS) · Hsinchu, Taiwan

Overview

TSMC fabricates the large majority of the world's sub-7 nm logic. FY2024 revenue was $90.08B (+30% YoY) on $29.76B capex, at a 56.1% gross margin (TSMC Q4 2024).

The economics

Energy & water

Position in the chain

Consumes wafers (Shin-Etsu), EUV tools (ASML), and gases; supplies dies + CoWoS packaging to fabless designers like NVIDIA.

Not publicly disclosed

Per-node wafer pricing and per-node energy/water — all node-specific figures here are analyst or company-average, flagged accordingly.