← Auto-Research BETA v0.1.0 / model silicon-stack
in_progress

Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

← all references

Analysis of the Electricity Consumption for the Production of Electronic-Grade Polysilicon (Fraunhofer ISE, on behalf of Wacker Chemie AG)

tier S
2025 · report
https://www.ise.fraunhofer.de/content/dam/ise/en/documents/publications/studies/25_en_ISE_Report_Analysis-of-the-Electricity-Consumption-for-the-Production-of-Electronic-Grade-Polysilicon.pdf ↗

Abstract

Analysis of the Electricity Consumption for the Production of Electronic-Grade Polysilicon (Fraunhofer ISE, on behalf of Wacker Chemie AG). Fetched by the auto-model research pass; the figures below are cited from this source in the model's flow, idiot-index, energetic-index, and market tabs.

Key facts

Reviewer note

Real source gathered during the extend-silicon-stack research pass (2026-06-21). Figures attributed to it in the model link back here.