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Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

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ASML

https://www.asml.com/ ↗

EUV lithography systems (sole supplier) · Veldhoven, Netherlands

Overview

ASML is the sole supplier of EUV lithography — the single hardest chokepoint in the leading-edge stack. FY2025: €32.7B revenue, €9.6B net income, 52.8% gross margin, with €8.2B of recurring service revenue (ASML Q4 2025).

The machines

Per-wafer cost

SemiAnalysis models ~$30–70 per wafer per EUV layer; a leading-edge wafer sees ~10–25 EUV layers ⇒ ~$300–1,500 of scanner-amortized EUV cost (SemiAnalysis). It reaches the wafer via tool depreciation inside TSMC's wafer price.

Position in the chain

Integrates Zeiss/Cymer/Trumpf into scanners sold to TSMC. See Inputs → EUV lithography.