← Auto-Research BETA v0.1.0 / model silicon-stack
in_progress

Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

Energetic idiot index

I_E = actual cradle-to-gate energy ÷ thermodynamic floor. The joules-based, "above Musk" lens: how far the actual energy to make a unit sits above the minimum the physics demands for the same atoms (mining, reduction, purification, crystal growth, fab). Each side carries a citation or a labelled estimate.

Full cradle-to-gate energy per leading-edge wafer

2,300×
medium confidence
Actual · Fab electricity per wafer (company avg)
Floor · Thermodynamic floor (Si in one wafer)

The full chip stack burns ~2,000–3,000× the thermodynamic minimum for its silicon — vast headroom, the energetic industrial-explosion signal.

Metallurgical silicon smelting (per kg Si)

high confidence
Actual · Submerged-arc furnace electricity
Floor · Reduction enthalpy ΔH

The smelting step is already close to its floor (~2×) — the silicon-winning chemistry is near-optimal. The waste is all downstream.

Siemens polysilicon purification (per kg)

78,000×
medium confidence
Actual · Electronic-grade Siemens energy
Floor · Ideal separation work
0.005 MJ est.

Purification is the single most thermodynamically wasteful step — ~78,000× the ideal separation work. The biggest energetic opportunity in the stack.