← Auto-Research BETA v0.1.0 / model silicon-stack
in_progress

Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

← all references

Ukraine, Neon, and Semiconductors (USITC Executive Briefing)

tier S
2022 · report
https://www.usitc.gov/publications/332/executive_briefings/ebot_decarlo_goodman_ukraine_neon_and_semiconductors.pdf ↗

Abstract

Ukraine, Neon, and Semiconductors (USITC Executive Briefing). Fetched by the auto-model research pass; the figures below are cited from this source in the model's flow, idiot-index, energetic-index, and market tabs.

Key facts

Reviewer note

Real source gathered during the extend-silicon-stack research pass (2026-06-21). Figures attributed to it in the model link back here.