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Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

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TSMC CoWoS Wafer ASP Reportedly Nears 7nm Levels; Advanced Packaging to Become a Key Profit Driver

tier A
2026 · press
https://www.trendforce.com/news/2026/04/28/news-tsmc-cowos-wafer-asp-reportedly-nears-7nm-levels-advanced-packaging-poised-to-become-a-key-profit-driver/ ↗

Abstract

TSMC CoWoS Wafer ASP Reportedly Nears 7nm Levels; Advanced Packaging to Become a Key Profit Driver. Fetched by the auto-model research pass; the figures below are cited from this source in the model's flow, idiot-index, energetic-index, and market tabs.

Key facts

Reviewer note

Real source gathered during the extend-silicon-stack research pass (2026-06-21). Figures attributed to it in the model link back here.