Abstract

ASML Dilemma / Die Size and Reticle Conundrum — Cost Model With Lithography Scanner Throughput (SemiAnalysis). Fetched by the auto-model research pass; the figures below are cited from this source in the model's flow, idiot-index, energetic-index, and market tabs.

Key facts

• High-NA EXE:5200B ~$57M/yr depreciation (7-yr life on ~$400M tool)
• 175 wph @ 75% uptime ≈ 1.15M wafers/yr
• ~$50/wafer/layer from depreciation alone (High-NA)
• Service ~$20-25M/yr adds ~$20/wafer; power 1.5 MW adds ~$0.6/wafer
• ~$70/wafer/layer total for the High-NA scanner
• A single High-NA exposure ~2.5x cost of a single Low-NA exposure
• High-NA cost-effective only when replacing a 3+ mask EUV multi-patterning sequence
• ~$350M capex per 100k wafer-starts/month; ~$70/wafer OpEx per EUV loop

Reviewer note

Real source gathered during the extend-silicon-stack research pass (2026-06-21). Figures attributed to it in the model link back here.