Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

What does it physically and economically take to make a leading-edge logic chip, end to end?

Leading-edge throughput

~12–13 M wafers / yr

TSMC shipped 12.9 M 12-inch-equiv wafers in 2024 (cited); leading-edge is a high-value subset.

Chain value

$200 → $18k → ~$30k+

Blank wafer ~$200 → patterned 3nm wafer ~$18k → finished accelerator ~$30k+ (with HBM + packaging).

Top idiot index

~60,000×

3nm wafer ASP ($18k) ÷ the raw silicon atoms in it (~$0.30). Far from the material floor.

Energetic idiot index

~2,300×

Full-stack energy/wafer (~2 MWh) ÷ thermodynamic floor (3.1 MJ). Purification alone is ~78,000×.

Supply-chain flow

ribbon = value added/wafer · node outline = company revenue · hover a flow · click a node → company

Global semiconductor market — size & growth

USD billions, total semiconductor revenue (WSTS/SIA) cite ↗ sia-2024-sales

Market CAGR (2015→2024)

~7.2% est.

2025 actual

$792B cite ↗ sia-2025-sales

Projected 2030

~$1.0T+ cite ↗ counterpoint-1t-2030

AI accelerator CAGR

~25% (GPU ~31%) cite ↗ mordor-ai-accelerators

Leading-edge node growth

>60%/yr cite ↗ mnm-advanced-process-nodes

Boundary: Cradle-to-gate: from mined quartz/carbon through fab + advanced packaging to a finished accelerator. Excludes board assembly, distribution, use-phase.

Discipline: every flow is a claim carrying a citation (cite) or a labelled estimate (est.). See the Idiot Index and References tabs.