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Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

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ASML's 2025 Revenue Up 16% YoY As Strong EUV Shipments Boost Systems and Service Performance (Counterpoint Research)

tier A
2026 · report
https://counterpointresearch.com/en/insights/asml-2025-revenue-up-16-yoy-as-strong-euv-shipments-boost-systems-and-service-performance ↗

Abstract

ASML's 2025 Revenue Up 16% YoY As Strong EUV Shipments Boost Systems and Service Performance (Counterpoint Research). Fetched by the auto-model research pass; the figures below are cited from this source in the model's flow, idiot-index, energetic-index, and market tabs.

Key facts

Reviewer note

Real source gathered during the extend-silicon-stack research pass (2026-06-21). Figures attributed to it in the model link back here.