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Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

← all references

Industry/academic data on semiconductor water use per 300mm wafer (via TSMC sustainability search synthesis & ScienceDirect LCA literature)

tier B
2023 · paper
https://www.sciencedirect.com/science/article/pii/S2666445323000041 ↗

Abstract

Industry/academic data on semiconductor water use per 300mm wafer (via TSMC sustainability search synthesis & ScienceDirect LCA literature). Fetched by the auto-model research pass; the figures below are cited from this source in the model's flow, idiot-index, energetic-index, and market tabs.

Key facts

Reviewer note

Real source gathered during the extend-silicon-stack research pass (2026-06-21). Figures attributed to it in the model link back here.