← Auto-Research BETA v0.1.0 / model silicon-stack
in_progress

Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

← all references

2026 Global Semiconductor Industry Outlook (Deloitte)

tier A
2026 · report
https://www.deloitte.com/us/en/insights/industry/technology/technology-media-telecom-outlooks/semiconductor-industry-outlook.html ↗

Abstract

2026 Global Semiconductor Industry Outlook (Deloitte). Fetched by the auto-model research pass; the figures below are cited from this source in the model's flow, idiot-index, energetic-index, and market tabs.

Key facts

Reviewer note

Real source gathered during the extend-silicon-stack research pass (2026-06-21). Figures attributed to it in the model link back here.