← Auto-Research BETA v0.1.0 / model silicon-stack
in_progress

Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

← all references

ASML Annual Report 2024

tier B
ASML Holding N.V. · 2024 · report
https://www.asml.com/en/investors/annual-report ↗

Abstract

(Scaffold stub — extract pending the research pass.) ASML's annual report: EUV/DUV systems shipped, average selling prices, R&D and service revenue. Used here to anchor the amortized per-wafer cost of EUV lithography; exact unit counts and ASPs to be extracted and verified before attribution.

Key claims

Reviewer notes

Scaffold extract. Slug resolves so the citation is wired; figures must be fetched and verified by the research pass before any number is sourced here.