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Leading-edge logic chip (300 mm wafer → packaged AI accelerator)

unit: Per 300 mm leading-edge logic wafer (~3–5 nm) for the front end; per finished accelerator package for the back end

← all references

Evaluation of energy consumption and thermal optimization strategies in Czochralski silicon crystal growth furnaces (Aalto University, study at Okmetic Oy)

tier A
2024 · paper
https://aaltodoc.aalto.fi/items/2e430e75-0b9f-49b5-ab6b-03e553e914da ↗

Abstract

Evaluation of energy consumption and thermal optimization strategies in Czochralski silicon crystal growth furnaces (Aalto University, study at Okmetic Oy). Fetched by the auto-model research pass; the figures below are cited from this source in the model's flow, idiot-index, energetic-index, and market tabs.

Key facts

Reviewer note

Real source gathered during the extend-silicon-stack research pass (2026-06-21). Figures attributed to it in the model link back here.